1. Field of the Invention
The present invention relates generally to methods for forming etched silicon layers within microelectronic fabrications. More particularly, the present invention relates to plasma etch methods for forming with attenuated plasma etch residue plasma etched silicon layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become more common in the art of microelectronic fabrication to employ plasma etch methods for forming etched silicon layers, including but not limited to etched monocrystalline silicon layers, etched polycrystalline silicon layers and etched amorphous silicon layers, within microelectronic fabrications.
Such plasma etch methods often employ plasma etchant gas compositions which upon plasma activation provide active bromine and/or chlorine containing etchant species, such as may be derived, for example and without limitation, from etchant gases including but not limited to bromine, hydrogen bromide, chlorine and/or hydrogen chloride. Similarly, such etched silicon layers formed within microelectronic fabrications may include, but are not limited to: (1) partially etched monocrystalline silicon semiconductor substrate layers having shallow and/or deep isolation and/or capacitive trenches etched therein as employed within semiconductor integrated circuit microelectronic fabrications, as well as; (2) fully etched and patterned polycrystalline silicon non-substrate layers which may be employed as: (a) patterned polysilicon conductor layers within microelectronic fabrications including but not limited to semiconductor integrated circuit microelectronic fabrications, as well as; (b) gate electrodes within field effect transistors (FETs) employed within semiconductor integrated circuit microelectronic fabrications.
Similarly, such etched silicon layers when formed within microelectronic fabrications while employing plasma etch methods which employ etchant gas compositions which upon plasma activation provide active bromine and/or chlorine containing etchant species are often formed in the presence of silicon containing dielectric layers, such as but not limited to silicon oxide dielectric layers, silicon nitride dielectric layers and silicon oxynitride dielectric layers. The silicon containing dielectric layers may be formed as plasma etch mask hard mask patterned silicon containing dielectric layers, or in the alternative as substrate layers, such as, for example and without limitation, as gate dielectric silicon containing dielectric layers formed beneath gate electrodes formed within field effect transistors (FETs) employed within semiconductor integrated circuit microelectronic fabrications.
While plasma etch methods for forming etched silicon layers for use within microelectronic fabrications are thus desirable and common within the art of microelectronic fabrication, plasma etch methods for forming etched silicon layers for use within microelectronic fabrications are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, it is known in the art of microelectronic fabrication that: (1) it is often difficult to reproducibly and controllably form while employing plasma etch methods etched silicon layers with attenuated residue formation (such as but not limited to attenuated particulate contamination residue formation) within microelectronic fabrications; and (2) in situations where the etched silicon layers are formed in the presence of silicon containing dielectric layers, it is often difficult to reproducibly and controllably form the etched silicon layers with enhanced selectivity of the plasma etch methods for the etched silicon layers with respect to the silicon containing dielectric layers.
It is thus towards the goal of providing for use when fabricating microelectronic fabrications plasma etch methods for reproducibly and controllably forming within microelectronic fabrications etched silicon layers with: (1) attenuated residue formation (such as but not limited to particulate contamination residue formation); and (2) enhanced selectivity of the plasma etch methods for the etched silicon layers with respect to silicon containing dielectric layers when those etched silicon layers are formed in the presence of silicon containing dielectric layers, that the present invention is directed.
Various plasma processing methods have been disclosed in the art of microelectronic fabrication for forming plasma processed microelectronic layers with desirable properties within microelectronic fabrications.
For example, Gupta et al., in U.S. Pat. No. 5,456,796, discloses a plasma processing method for attenuating particulate generation and deposition upon a substrate employed within a microelectronic fabrication when processing the substrate employed within the microelectronic fabrication while employing the plasma processing method. The plasma processing method employs: (1) a rapid increase of a plasma power within a plasma reactor chamber to a high plasma power level prior to introduction of the substrate into a plasma reactor chamber to thus provide for effective cleaning of the plasma reactor chamber prior to introduction of the substrate into the plasma reactor chamber, in conjunction with; (2) a slower increase of the plasma power within the plasma reactor chamber subsequent to introduction of the substrate into the plasma reactor chamber in order to avoid circulation of particles within the plasma reactor chamber which would otherwise settle upon the substrate.
In addition, Saito et al., in U.S. Pat. No. 5,681,424, disclose a plasma processing method for cleaning a plasma reactor chamber within which is plasma etched a silicon layer formed over a substrate while employing a hydrogen bromide containing etchant gas composition, while simultaneously dissipating an electrostatic charge formed upon the substrate incident to use within a plasma apparatus employed within the plasma processing method of an electrostatic chuck for securing the substrate within the plasma reactor chamber. The plasma processing method employs an oxygen containing etchant gas composition for simultaneously cleaning the reactor chamber and dissipating the electrostatic charge formed upon the substrate.
Further, Leung et al., in U.S. Pat. No. 5,705,080, disclose a plasma processing method for cleaning deposits from within a reactor chamber, including but not limited to a plasma reactor chamber, without damaging within the reactor chamber reactor components which are otherwise sensitive to the plasma processing method. The plasma processing method employs covering within the reactor chamber components which are otherwise sensitive to the plasma processing method prior to cleaning the deposits from within the reactor chamber while employing the plasma processing method.
Still further, Murugesh et al., in U.S. Pat. No. 5,811,356, disclose a plasma processing method and a plasma processing apparatus which provide for a reduced concentration of mobile ions and metal contaminants within a reactor chamber so that there may be fabricated within the reactor chamber microelectronic layers, particularly microelectronic dielectric layers, with enhanced reliability. The method employs, when seasoning the reactor chamber while employing the plasma processing method and the plasma processing apparatus, a bias radio frequency power density of greater than 0.051 watts per square millimeter and a seasoning time of greater than about 30 seconds.
Finally, Gupta, in U.S. Pat. No. 5,824,375, discloses a plasma processing method and a plasma processing apparatus for reducing fluorine and other sorbable contaminants in a plasma reactor chamber employed within a chemical vapor deposition (CVD) method, such as but not limited to a plasma enhanced chemical vapor deposition (PECVD) method. The plasma processing method and the plasma processing apparatus employ an inert plasma treatment of the plasma reactor chamber after cleaning the plasma reactor chamber while employing a fluorine containing plasma etch method and prior to forming within the plasma reactor chamber while employing a plasma deposition method a passivating seasoning layer within the plasma reactor chamber.
Desirable in the art of microelectronic fabrication are additional plasma etch methods and materials which may be employed for reproducibly and controllably forming with attenuated residue etched silicon layers within microelectronic fabrications with enhanced selectivity of the plasma etch methods for the etched silicon layers with respect to silicon containing dielectric layers when the etched silicon layers are formed in the presence of silicon containing dielectric layers.
It is towards the foregoing objects that the present invention is directed.
A first object of the present invention is to provide a plasma etch method for reproducibly and controllably forming an etched silicon layer within a microelectronic fabrication.
A second object of the present invention is to provide a plasma etch method in accord with the first object of the present invention, where the etched silicon layer is reproducibly and controllably formed with attenuated residue (such as but not limited to particulate contamination residue).
A third object of the present invention is to provide a plasma etch method in accord with the first object of the present invention and the second object of the present invention, where the plasma etch method reproducibly and controllably exhibits enhanced selectivity for the etched silicon layer with respect to a silicon containing dielectric layer when the etched silicon layer is formed in the presence of the silicon containing dielectric layer within the microelectronic fabrication.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention and the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a plasma etch method for forming an etched silicon layer. To practice the method of the present invention, there is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species, wherein within the plasma etch method: (1) a cleaned plasma reactor chamber is seasoned to provide a seasoned plasma reactor chamber having a seasoning polymer layer formed therein; (2) the first silicon layer is etched to form the etched first silicon layer within the seasoned plasma reactor chamber; and (3) the seasoning polymer layer is cleaned from the seasoned plasma reactor chamber to provide the cleaned plasma reactor chamber after etching the first silicon layer to form the etched first silicon layer within the seasoned plasma reactor chamber, prior to etching a second silicon layer to form an etched second silicon layer formed over a second substrate within cleaned plasma reactor chamber while employing the plasma etch method in accord with (1), (2) and (3).
The present invention provides a plasma etch method for reproducibly and controllably forming an etched silicon layer within a microelectronic fabrication, where the etched silicon layer is formed with attenuated residue (such as but not limited to particulate residue) and where the plasma etch method exhibits enhanced selectivity for the etched silicon layer with respect to a silicon containing dielectric layer when the etched silicon layer is formed in the presence of the silicon containing dielectric layer within the microelectronic fabrication. The present invention realizes the foregoing objects by employing within the present invention: (1) a cleaned plasma reactor chamber seasoning to provide a seasoned plasma reactor chamber having a seasoning polymer layer formed therein; (2) a single substrate silicon layer etching within the seasoned plasma reactor chamber; and (3) a cleaning of the seasoning polymer layer from the seasoned plasma reactor chamber to provide the cleaned plasma reactor chamber, prior to etching a second silicon layer to form an etched second silicon layer formed over a second substrate while employing the preceding steps (1), (2) and (3).
The method of the present invention is readily commercially implemented. The present invention employs an apparatus which is generally conventional in the art of microelectronic fabrication. Since it is a process control and materials selection which provides at least in part the present invention, rather than the existence of methods and apparatus which provides the present invention, the method of the present invention is readily commercially implemented.